Aegis: The First Fully Open-Source FPGA — From Silicon Design to Tapeout

Aegis — Open-Source FPGA From the Ground Up

A new project called Aegis claims to be the first fully open-source FPGA, with everything from the silicon fabric design to the complete toolchain available under open licenses. Unlike previous efforts that reverse-engineered proprietary chips or built tools around closed silicon, Aegis starts from the other end.

The Problem It Solves

Existing open-source FPGA efforts fall into two categories:

1. Reverse engineering — Projects like IceStorm and Apicula reverse-engineer proprietary architectures
2. Open tooling, closed silicon — Yosys and nextpnr build toolchains around proprietary chips

In all cases, the silicon itself has remained proprietary. Aegis breaks this pattern entirely.

Technical Details

The first Aegis device, Terra 1, targets GlobalFoundries' 180MCU process via the wafer.space shuttle service:

Complete Toolchain

Each Aegis device ships with a full FPGA toolchain:

• Yosys — Synthesizes Verilog to Aegis cells
• nextpnr-aegis — Place and route on the fabric
• terra_1-pack — Generates bitstreams
• terra_1-sim — Simulates loaded bitstreams

Full Tapeout Pipeline

Perhaps most impressively, the project provides a complete RTL-to-GDS pipeline for actual chip fabrication:

nix build .#terra-1-tapeout

The tapeout supports both GF180MCU (via wafer.space) and Sky130 PDKs.

Architecture

The FPGA fabric is generated by ROHD (a Dart HDL framework) and follows Xilinx-style conventions:

• CLB: LUT4 + D flip-flop + MUXCY carry chain
• Tile: CLB + 4-directional routing muxes
• BRAM: Dual-port 128x8 block RAM
• DSP: 18x18 multiply-accumulate with optional pipeline
• IO: Bidirectional pad with registers
• SerDes: Protocol-agnostic serializer/deserializer

Why This Matters

Open-source silicon is a frontier that could democratize hardware development. By providing the full stack — from fabric design to fabrication pipeline — Aegis enables:

1. Custom chip design without proprietary EDA tools
2. Educational access to real FPGA silicon
3. Community-driven hardware innovation
4. Verification and auditability of the entire hardware stack

Source: GitHub (MidstallSoftware/aegis), Hacker News